MC68HC68R1 Datasheet - Motorola

MC68HC68R1 8-BIT SERIAL STATIC RAMs

CHIP ENABLE AND SLAVE SELECT (CE AND SS) A high level on the CE pin, coincident with a low level on the SS pin, is required for the RAM serial interface logic to become enabled. The device is held in the reset state if either CE is low or SS is high. SERIAL CLOCK (SCK) This clock input is used to sy.

® MOTOROLA Advance Information 8-BIT SERIAL STATIC RAMs The MC68HC68Rl and MC68HC68R2 are serially organized 128-word (MC68HC68Rl) or 256-word (MC68HC68R2) by 8-bit static random access memories (RAMs). These RAMs are intended for use in systems where minimum package and interconnect size, low power, and simplicity of use are desirable; for example, in systems utilizing synchronous serial 3-wire (clock, data in, data out) interfaces. Interface can I be made with the MC68HC05D2 without additional.

MC68HC68R1 Datasheet (81.25 KB)