* Five Outputs (Q0
* Q4) with Output
* Output Skew < 500 ps each being phase and frequency locked to the SYNC input
* The phase variation from part
* to
* part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPD specification, which
MC88LV915 Datasheet (127.34 KB)
MC88LV915
Motorola
127.34 KB
Low skew cmos pll clock driver.
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage Low Skew CMOS PLL Clock Driver, 3-State The MC88LV915T Clock Driver utilizes phase locked .
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