* of bus contention conditions is necessary during read and write cycles. 3. All write cycle timings are referenced from the last valid address to the first transitioning address. 4. Transition is measured 200 mV from steady
* state voltage. 5. This parameter is sampled and not 100% tested. 6.
MCM6926A Datasheet (122.90 KB)
MCM6926A
Motorola
122.90 KB
128k x 9 bit fast static random access memory.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM6926A/D
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MCM6926A
128K x 8 Bit Fast Static Random Access Memor.
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