MPC9315 Datasheet - Motorola

MPC9315 2.5V and 3.3V CMOS PLL Clock Generator/Driver

The MPC9315 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation requires a connection of one of the device outputs to the selected feedback (FB0 or FB1) input to close the PLL feedback path. The reference clock frequency and the output divi.

www.DataSheet4U.com MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order Number: MPC9315/D Rev 2, 02/2002 2.5V and 3.3V CMOS PLL Clock Generator and Driver The MPC9315 is a 2.5V and 3.3V compatible, PLL based clock generator designed for low-skew clock distribution in low-voltage mid-range to high-performance telecom, networking and computing applications. The MPC9315 offers 8 low-skew outputs and 2 selectable inputs for clock redundancy. The outputs are configurable and support 1:1, 2:1, 4:1, 1:2 and.

MPC9315 Features

* Fully integrated PLL supports spread spectrum clocking

* Supports applications requiring clock redundancy

* Max. output skew of 120 ps (80 ps within one bank)

* Selectable output configurations (1:1, 2:1, 4:1, 1:2, 1:4 frequency ratios)

* 2 selectable LVCMO

MPC9315_Motorola.pdf