MPC9600 - LOW VOLTAGE 2.5 V AND 3.3 V CMOS PLL CLOCK DRIVER

Product Overview

Motorola

Datasheet Details

Part number	MPC9600
Manufacturer	Motorola
File Size	365.84 KB
Description	LOW VOLTAGE 2.5 V AND 3.3 V CMOS PLL CLOCK DRIVER
Datasheet	MPC9600 Datasheet
Additional preview pages of the MPC9600 datasheet.

Product details

Description

Differential reference clock frequency input Reference clock input PLL feedback clock input Bank A outputs Bank B outputs Bank C outputs Differential feedback output Reference clock input select Selection of bank A output frequency Selection of bank B output frequency Selection of bank C output frequency Selection of feedback frequency Output enable Analog power supply and PLL bypass.

Features

Multiplication of input frequency by 2, 3, 4 and 6.
Distribution of output frequency to 21 outputs organized in three output banks: QA0-QA6, QB0-QB6, QC0-QC6, each fully selectable.
Selectable output frequency range is 50 to 100 MHz and 100 to 200 MHz.
Selectable input frequency range is 16.67 to 33 MHz and 25 to 50 MHz.
LVCMOS outputs.
Outputs disable to high impedance (except QFB).
LVCMOS or LVPECL reference clock options.

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Published: Jul 5, 2008 |