MPC962308 Datasheet - Motorola

MPC962308 3.3 V Zero Delay Buffer

The MPC962308 has two banks of four outputs each which can be controlled by the select inputs as shown in Table 1. Select Input Decoding. Bank B can be tristated if all of the outputs are not required. The select inputs also allow the input clock to be directly applied to the output for chip and sys.

Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order number: MPC962308 Rev 3, 08/2004 3.3 V Zero Delay Buffer The MPC962308 is a 3.3 V Zero Delay Buffer designed to distribute high-speed clocks in PC, workstation, datacom, telecom and other high-performance applications. The MPC962308 uses an internal PLL and an external feedback path to lock its low-skew clock output phase to the reference clock phase, providing virtually zero propagation delay. The input-to-output skew is.

MPC962308 Features

* 1:8 outputs LVCMOS zero-delay buffer Zero input-output propagation delay, adjustable by the capacitive load on FBK input Multiple Configurations, see

MPC962308 Datasheet (447.95 KB)