UPC4092 Datasheet (NEC) - J-FET INPUT LOW-OFFSET DUAL OPERATIONAL AMPLIFIER

UPC4092, J-FET INPUT LOW-OFFSET DUAL OPERATIONAL AMPLIFIER

DATA SHEET BIPOLAR ANALOG INTEGRATED CIRCUIT µPC4092 J-FET INPUT LOW-OFFSET DUAL OPERATIONAL AMPLIFIER The µPC4092 dual operational amplifier offers high input impedance, low offset voltage, high slew rate, and stable AC operating characteristics.

NEC's unique high-speed PNP transistor (f T = 300 MHz) in the output stage solves the oscillation problem of current sinking with a large capacitive load.

Zener-zap resistor trimming in the input stage produces excellent offset voltage and temperat

UPC4092 Features

* Stable operation with 10000 pF capacitive load

* Low input offset voltage ±3 mV (MAX.) ±7 µV/°C (TYP.) temperature drift

* Very low input bias and offset currents

* Low noise : en = 19 nV/ √Hz (TYP.)

* Output short circuit protection

* High input imp