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S7I643684M Datasheet - NETSOL

S7I643684M 2Mx36 & 4Mx18 DDRII CIO BL4 SRAM

The S7I643684M and S7I641884M are 75,497,472-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 2,097,152 words by 36bits for S7I643684M and 4,194,304 words by 18 bits for S7I641884M. Address, data inputs, and all control signals are synchronized to the input clock (K or K).

SSSS7777II66II6644441331866888884444MMMM Preliminary Preliminary 22MMxx3366 && 44MMxx1188 DDDDRRIIII CCIIOO BBLL44 SSRRAAMM 72Mb DDRII CIO BL4 SRAM Specification 165FBGA with Pb & Pb Free (ROHS Compliant) NETSOL RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all i.

S7I643684M Features

* 1.8V+0.1V/-0.1V Power Supply.

* DLL circuitry for wide output data valid window and future fre- quency scaling.

* I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.

* Pipelined, double-data rate operation.

* Common data input/outp

S7I643684M Datasheet (410.13 KB)