S7I161884M Datasheet - NETSOL

S7I161884M 512Kx36 & 1Mx18 DDRII CIO BL4 SRAM

The S7I163684M and S7I161884M are 18,874,368-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for S7I163684M and 1,048,576 words by 18 bits for S7I161884M. Address, data inputs, and all control signals are synchronized to the input clock (K or K). .

SS77I1I16633668844MM SS77I1I16611888844MM 512Kx36 & 1Mx18 DDRII CIO BL4 SRAM 18Mb DDRII CIO BL4 SRAM Specification 165FBGA with Pb & Pb Free (ROHS Compliant) NETSOL RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and.

S7I161884M Features

* 1.8V+0.1V/-0.1V Power Supply.

* DLL circuitry for wide output data valid window and future fre- quency scaling.

* I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O

* Pipelined, double-data rate operation.

* Common data input/outp

S7I161884M Datasheet (366.17 KB)