S7I321882M Datasheet - NETSOL

S7I321882M 1Mx36 & 2Mx18 DDRII CIO BL2 SRAM

The S7I323682M and S7I321882M are 37,748,736-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 1,048,576 words by 36bits for S7I323682M and 2,097,152 words by 18 bits for S7I321882M. Address, data inputs, and all control signals are synchronized to the input clock (K or K).

SSSS7777II33II3322221331866888882222MMMM 11MMxx3366 && 22MMxx1188 DDDDRRIIII CCIIOO BBLL22 SSRRAAMM 36Mb DDRII CIO BL2 SRAM Specification 165FBGA with Pb & Pb Free (ROHS Compliant) NETSOL RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed her.

S7I321882M Features

* 1.8V+0.1V/-0.1V Power Supply.

* DLL circuitry for wide output data valid window and future fre- quency scaling.

* I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O

* Pipelined, double-data rate operation.

* Common data input/outp

S7I321882M Datasheet (364.88 KB)