* Common clock and master reset
* Eight positive edge-triggered D-type flip-flops
* Complies with JEDEC standard no. 7A
* Input levels:
* For 74HC377: CMOS level
* For 74HCT377: TTL level
* ESD protection:
* HBM JESD22-A114F exceeds 2000 V
* MM JESD22-A115-A excee
74HCT377 Datasheet (134.23 KB)
74HCT377
134.23 KB
Octal d-type flip-flop.
74HC377; 74HCT377
Octal D-type flip-flop with data enable; positive-edge trigger
Rev. 3
* 25 September 2013
Product data sheet
1. General .
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