* of a single U.D. The U.D. provides a fast output signal FF at output OFF, which can have a phase jitter of ± 1 system input period, to allow fast frequency locking. The slow output signal FS at output OFS, which is jitter-free, is used for fine phase control at a lower speed. Fig.1 Pinning diagram.
HEF4751V Datasheet (151.56 KB)
HEF4751V
151.56 KB
Universal divider.
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HE.
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