MPC8560 Datasheet - NXP

MPC8560 Integrated Communications Processor Reference Manual

Reset, Clocking, and Initialization Part II *e500 Core Complex and L2 Cache e500 Core Complex Overview e500 Register Summary L2 Look-Aside Cache/SRAM Part III *Memory and I/O Interfaces e500 Coherency Module DDR Memory Controller Programmable Interrupt Controller I2C Interface Local B.

MPC8560 PowerQUICC III™ Integrated Communications Processor Reference Manual MPC8560RM Rev. 1 07/2004 How to Reach Us: USA/Europe/Locations Not Listed: Freescale Semiconductor Literature Distribution Center P.O. Box 5405, Denver, Colorado 80217 1-480-768-2130 (800) 521-6274 Japan: Freescale Semiconductor Japan Ltd. Technical Information Center 3-20-1, Minami-Azabu, Minato-ku Tokyo 106-8573, Japan 81-3-3440-3569 Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. 2 Dai King Street Tai Po Indust.

MPC8560-NXP.pdf