PCF85053A Datasheet PDF - NXP Bootable CPU RTC Specs

PCF85053A - Bootable CPU RTC

Datasheet Summary

Description

The PCF85053A is a CMOS Real-Time Clock (RTC) and calendar optimized for low power consumption and automatic switching to battery on primary power loss.

Featuring clock output, ALRT (interrupt) output and 128 bytes of battery backup SRAM.

The PCF85053A includes two I2C buses.

Features

Voltage range addresses common supply rails.
VDD supply voltage from 1.7 V to 3.6 V.
VBAT battery supply voltage from 1.55 V to 3.6 V.
Two independent I2C interfaces with up to 400 kHz speed.
Primary I2C bus with Read/write capability on RTC and SRAM registers.
Secondary I2C bus with read/write capability on RTC and SRAM registers enabled by primary I2C.
Both I2C interface supports clock timeout of 35 ms max.
Crystal compat.

Datasheet Details

Part number	PCF85053A
Manufacturer	NXP
File Size	653.62 KB
Description	Bootable CPU RTC
Datasheet	PCF85053A Datasheet
Additional preview pages of the PCF85053A datasheet.

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Full PDF Text Transcription

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PCF85053A Bootable CPU RTC with two I2C buses, 128 byte SRAM and alarm function Rev. 1.1 — 10 September 2024 Product data sheet 1 General description The PCF85053A is a CMOS Real-Time Clock (RTC) and calendar optimized for low power consumption and automatic switching to battery on primary power loss. Featuring clock output, ALRT (interrupt) output and 128 bytes of battery backup SRAM. The PCF85053A includes two I2C buses. The primary I2C bus has the read/ write capability on RTC and SRAM registers. The second I2C bus also can read/write most registers with the control bits set by primary I2C controller. The PCF85053A offers clock output calibration-related registers such as crystal CL (capacitive load) configuration and offset register setting.

Published: Sep 14, 2024 |