Datasheet Specifications
- Part number
- PCK953
- Manufacturer
- NXP ↗
- File Size
- 71.10 KB
- Datasheet
- PCK953_PhilipsSemiconductors.pdf
- Description
- 50-125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver
Description
INTEGRATED CIRCUITS PCK953 50 *125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver Product specification Supersedes data of 2000 Oct 25 IC.
Features
* make the PCK953 ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The MR/OE input pin will reset the internal counters and 3-State the output buffers when driven HIGH. The PCK953 is fully 3.3 V compatible and requirApplications
* info section). PLL INPUT REFERENCE CHARACTERISTICS Tamb = 0 to 70°C SYMBOL fref frefDC PARAMETER Reference input frequency Reference input duty cycle CONDITION MIN 20 25 MAX 125 75 UNIT MHz % NOTE: 1. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider. APCK953 Distributors
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