* make the PCK953 ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The MR/OE input pin will reset the internal counters and 3-State the output buffers when driven HIGH. The PCK953 is fully 3.3 V compatible and requir
PCK953
71.10 KB
50-125 mhz pecl input/9 cmos output 3.3 v pll clock driver.
INTEGRATED CIRCUITS
PCK953 50
*125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver
Product specification Supersedes data of 2000 Oct 25 IC.
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