PCK953 Datasheet - NXP

PCK953 50-125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver

The PCK953 is a 3.3 V compatible, PLL-based clock driver device targeted for high performance clock tree designs. With output frequencies of up to 125 MHz, and output skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs. The devices employ a fully differential PLL design to.

PCK953 Features

* make the PCK953 ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The MR/OE input pin will reset the internal counters and 3-State the output buffers when driven HIGH. The PCK953 is fully 3.3 V compatible and requir

PCK953 Datasheet (71.10 KB)