S32R372 Datasheet (NXP)

S32R372, 32-bit CPU

9 9.2 LINFlexD timing specifications39 3.2 Format 9 9.3 I2C timing 39 3.3 Fields 9 10 Debug modules40 4 General 11 10.1 JTAG/CJTAG interface timing 40 4.1 Introduction 11 10.2 Nexus Aurora debug port timing43 4.2 Absolute maximum ratings 11 11 WKPU/NMI timing specifications44 4.3 Opera

S32R372 Features

* Dual issue computation cores: Power Architecture® e200z7 32-bit CPU

* 1.3 MB on-chip code flash memory (FMC flash memory) with ECC

* 1 MB on-chip SRAM with ECC

* RADAR processing

* Signal Processing Toolbox (SPT) for RADAR signal processing acceleration