NT5CB512M4BN Datasheet (Nanya) - 2Gb DDR3 SDRAM B-Die

NT5CB512M4BN, 2Gb DDR3 SDRAM B-Die

The 2Gb Double-Data-Rate-3 (DDR3) DRAMs is a high-speed CMOS Double Data Rate32 SDRAM containing 2,147,483,648 bits.

It is internally configured as an octal-bank DRAM.

The 2Gb chip is organized as 64Mbit x 4 I/O x 8 bank, 32Mbit x 8 I/O x 8 bank or 16Mbit x 16 I/O x 8 bank device.

These synchronous

NT5CB512M4BN Features

* and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and  falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchrono