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NT5CC256M8FN, NT5CB256M8FN Datasheet - Nanya

NT5CC256M8FN - Industrial and Automotive DDR3(L) 2Gb SDRAM

The 2Gb Double-Data-Rate-3 (DDR3(L)) is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAMs. The 2Gb chip is organized as 32Mbit x 8 I/Os x 8 banks or 16Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed double.

NT5CC256M8FN Features

* JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM

* Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via ext

NT5CB256M8FN-Nanya.pdf