NT5CC256M8GN Datasheet, G-die, Nanya

NT5CC256M8GN Features

• G-die and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK risin

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NT5CC256M8GN

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Nanya

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📄 Datasheet

Description:

2gb ddr3 sdram g-die. The 2Gb Double-Data-Rate-3 (DDR3) DRAMs is a high-speed CMOS Double Data Rate32 SDRAM containing 2,147,483,648 bits. It is internally

NT5CC256M8GN Application

• Applications The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a p

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NT5CC256M8GN

Nanya

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