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NT5CC512M8CN Datasheet - Nanya

NT5CC512M8CN Industrial and Automotive DDR3(L) 4Gb SDRAM

The 4Gb Double-Data-Rate-3 (DDR3(L)) DRAM is a high-speed CMOS SDRAM containing 4,294,967,296 bits. It is internally configured as an octal-bank DRAM. The 4Gb chip is organized as 64Mbit x 8 I/O x 8 banks and 32Mbit x16 I/O x 8 banks. These synchronous devices achieve high speed double-data-rate tr.

NT5CC512M8CN Features

* JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/ ) - Double-data rate on DQs, DQS and DM

* Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via ex

NT5CC512M8CN Datasheet (3.88 MB)