NT5CC512M8DN - Industrial and Automotive DDR3(L) 4Gb SDRAM

Nanya

Datasheet Details

Part number	NT5CC512M8DN
Manufacturer	Nanya
File Size	3.37 MB
Description	Industrial and Automotive DDR3(L) 4Gb SDRAM
Datasheet	NT5CC512M8DN-Nanya.pdf

JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM.
Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes.
Power Saving Mode - Partial Array Self Refresh (PASR)1 - Power Down Mode.
Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (2.

📁 NT5CC512M8DN Similar Datasheet

Other Datasheets by Nanya

Published: Oct 17, 2018 |