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54F273 - Octal D Flip-Flop

Datasheet Summary

Description

The ’F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously The register is fully edge-triggered The state of each D input one setup time before the LOW-to

Features

  • Y Ideal buffer for MOS microprocessor or memory Y Eight edge-triggered D flip-flops Y Buffered common clock Y Buffered asynchronous Master Reset Y See ’F377 for clock enable version Y See ’F373 for transparent latch version Y See ’F374 for TRI-STATE version Y Guaranteed 4000V minimum ESD protection Commercial 74F273PC 74F273SC (Note 1) 74F273SJ (Note 1) Military 54F273DM (Note 2) 54F273FM (Note 2) 54F273LM (Note 2) Package Number N20A J20A M20B M20D W20A E20A Package.

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54F 74F273 Octal D Flip-Flop Obsolete May 1995 54F 74F273 Octal D Flip-Flop General Description The ’F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously The register is fully edge-triggered The state of each D input one setup time before the LOW-to-HIGH clock transition is transferred to the corresponding flip-flop’s Q output All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements Features Y Ideal buffer for MOS microprocessor or memory Y Eight edg
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