74C2526 Datasheet - National Semiconductor

74C2526 1-to-8 Minimum Skew Clock Driver

On the multiplexed clock device the SEL pin is used to determine which CLKn input will have an active effect on the outputs of the circuit When SEL e 1 the CLK1 input is selected and when SEL e 0 the CLK0 input is selected The non-selected CLKn input will not have any effect on the logical output le.

CGS74C2525 CGS74CT2525 CGS74C2526 CGS74CT2526 1-to-8 Minimum Skew Clock Driver September 1995 CGS74C2525 CGS74CT2525 CGS74C2526 CGS74CT2526 1-to-8 Minimum Skew Clock Driver The CGS ’C CT2525 is a minimum skew clock driver with one input driving eight outputs specifically designed for signal generation and clock distribution applications The ’2525 is designed to distribute a single clock to eight separate receivers with low skew across all outputs during both the tPLH and tPHL transit.

74C2526 Features

* Y Y Y Y Y Y Y Y Y These CGS devices implement National’s FACTTM family Ideal for signal generation and clock distribution Guaranteed pin to pin and part to part skew Multiplexed clock input (’2526) Guaranteed 2 kV minimum ESD protection Symmetric output current drive of 24 mA for IOL IOH ’CT has T

74C2526 Datasheet (170.20 KB)