CD4035BM - 4-Bit Parallel-In/Parallel-Out Shift Register

National Semiconductor

CD4035BM Datasheet Preview — Preview of CD4035BM PDF

Datasheet Details

Part number	CD4035BM
Manufacturer	National Semiconductor ↗
File Size	139.98 KB
Description	4-Bit Parallel-In/Parallel-Out Shift Register
Datasheet	CD4035BM_NationalSemiconductor.pdf

CD4035BM Product details

Description

The CD4035B 4-bit parallel-in parallel-out shift register is a monolithic complementary MOS (CMOS) integrated circuit constructed with P- and N-channel enhancement mode transistors This shift register is a 4-stage clocked serial register having provisions for synchronous parallel inputs to each stage and serial inputs to the first stage via JK logic Register stages 2 3 and 4 are coupled in a serial ‘‘D’’ flipflop configuration when the register is in the serial mode (parallel serial control low)

Features

Y Y Y Y Y Y Y Y Y Y Y Y Wide supply voltage range 3 0V to 15V High noise immunity 0 45 VDD (typ ) Low power TTL Fan out of 2 driving 74L compatibility or 1 driving 74LS 4-stage clocked operation Synchronous parallel entry on all 4 stages JK inputs on first stage Asynchronous true complement control on all outputs Reset control Static flip-flop operation master slave configuration Buffered outputs Low power dissipation 5 mW (typ ) (ceramic) High speed to 5 MHz.

📁 CD4035BM Similar Datasheet

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Published: Mar 23, 2005 |