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DM54LS73A Datasheet - National Semiconductor

DM54LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops

This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops on the falling edge of the clock pulse The clock triggering occurs at a voltage level and is not directly related to the transition time of the negat.

DM54LS73A_NationalSemiconductor.pdf

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Datasheet Details

Part number:

DM54LS73A

Manufacturer:

National Semiconductor

File Size:

139.87 KB

Description:

Dual negative-edge-triggered master-slave j-k flip-flops.

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DM54LS73A DM54LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops National Semiconductor

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