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DM7474 - Dual Positive-Edge-Triggered D Flip-Flops

Download the DM7474 datasheet PDF. This datasheet also covers the DM7474M variant, as both devices belong to the same dual positive-edge-triggered d flip-flops family and are provided as variant models within a single manufacturer datasheet.

General Description

This device contains two independent positive-edge-triggered D flip-flops with complementary outputs The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse The triggering occurs at a voltage level and is not directly related to the transition time

Key Features

  • Y Alternate Military Aerospace device (5474) is available Contact a National Semiconductor Sales Office Distributor for specifications Connection Diagram Dual-In-Line Package TL F 6526.
  • 1 Order Number 5474DMQB 5474FMQB DM5474J DM5474W DM7474M or DM7474N See NS Package Number J14A M14A N14A or W14B Function Table Inputs Outputs PR CLR CLK D Q Q LH X XH L HL X XL H LL X XH H H H u HH L H H u LL H HH L X Q0 Q0 H e High Logic Level X e Either Low or High Logic Level L e.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DM7474M_NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription for DM7474 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for DM7474. For precise diagrams, and layout, please refer to the original PDF.

5474 DM5474 DM7474 Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs June 1989 5474 DM5474 DM7474 Dual Positive-Edge-Triggered D Flip-...

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puts June 1989 5474 DM5474 DM7474 Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D flip-flops with complementary outputs The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock The data on the D input may be changed while the clock is low or high without affecting the outputs as long as the data setup and hold times are not violated