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DM7474 - Dual Positive-Edge-Triggered D Flip-Flops

This page provides the datasheet information for the DM7474, a member of the DM7474M Dual Positive-Edge-Triggered D Flip-Flops family.

Description

This device contains two independent positive-edge-triggered D flip-flops with complementary outputs The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse The triggering occurs at a voltage level and is not directly related to the transition time

Features

  • Y Alternate Military Aerospace device (5474) is available Contact a National Semiconductor Sales Office Distributor for specifications Connection Diagram Dual-In-Line Package TL F 6526.
  • 1 Order Number 5474DMQB 5474FMQB DM5474J DM5474W DM7474M or DM7474N See NS Package Number J14A M14A N14A or W14B Function Table Inputs Outputs PR CLR CLK D Q Q LH X XH L HL X XL H LL X XH H H H u HH L H H u LL H HH L X Q0 Q0 H e High Logic Level X e Either Low or High Logic Level L e.

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📁 Similar Datasheet

  • DM7474 - Dual Positive-Edge-Triggered D-Type Flip-Flop (Fairchild Semiconductor)
  • DM7474M - Dual Positive-Edge-Triggered D-Type Flip-Flop (Fairchild Semiconductor)
  • DM7474N - Dual Positive-Edge-Triggered D-Type Flip-Flop (Fairchild Semiconductor)
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Other Datasheets by National Semiconductor
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  • DM7400 - Quad 2-Input NAND Gates
  • DM7401 - Quad 2-Input NAND Gates with Open-Collector Outputs
  • DM7402 - Quad 2-Input NOR Gates
  • DM7404 - Hex Inverting Gates
  • DM7405 - (DM5405 / DM7405) Hex Inverters

Full PDF Text Transcription

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5474 DM5474 DM7474 Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs June 1989 5474 DM5474 DM7474 Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D flip-flops with complementary outputs The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock The data on the D input may be changed while the clock is low or high without affecting the outputs as long as the data setup and hold times are not violated A low logic level on the preset or clear inputs will set or reset
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