Description
The DP8420A 21A 22A dynamic RAM controllers provide a low cost single chip interface between dynamic RAM and all 8- 16- and 32-bit systems The DP8420A 21A 22A generate all the required access control signal timing for DRAMs An on-chip refresh request clock is used to automatically refresh the DRAM array Refreshes and accesses are arbitrated on chip If necessary a WAIT or DTACK output inserts wait states into system access cycles including burst mode accesses RAS low time during refreshes and RAS
Features
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On chip high precision delay line to guarantee critical DRAM access timing parameters microCMOS process for low power High capacitance drivers for RAS CAS WE and DRAM address on chip On chip support for nibble page and static column DRAMs Byte enable signals on chip allow byte writing in a word size up to 32 bits with no external logic Selection of controller speeds 20 MHz and 25 MHz On board Port A Port B (DP8422A only) refresh arbitration logic Direct interface to all m.