DS90CF383 Datasheet (National Semiconductor)

DS90CF383, +3.3V LVDS Transmitter

The DS90CF383 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams.

A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link.

Every cycle of the transmit clock 28 bits of input data are sampled and

DS90CF383 Features

* n n n n n n n n n n n n n n n n 20 to 65 MHz shift clock support Single 3.3V supply Chipset (Tx + Rx) power consumption < 250 mW (typ) Power-down mode ( < 0.5 mW total) Single pixel per clock XGA (1024x768) ready Supports VGA, SVGA, XGA and higher addressability. Up to 227 Megabytes/sec bandwidth Up