Description
The DS90CF384A receiver converts the four LVDS data streams (Up to 1.8 Gbps throughput or 227 Megabytes/sec bandwidth) back into parallel 28 bits of CMOS/TTL data (24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL).
Features
- n n n n n n n n n n n 20 to 65 MHz shift clock support 50% duty cycle on receiver output clock Best.
- in.
- Class Set & Hold Times on RxOUTPUTs Rx power consumption < 142 mW (typ) @65MHz Grayscale Rx Power-down mode < 200µW (max) ESD rating > 7 kV (HBM), > 700V (EIAJ) Supports VGA, SVGA, XGA and Dual Pixel SXGA. PLL requires no external components Compatible with TIA/EIA-644 LVDS standard Low profile 56-lead or 48-lead TSSOP package DS90CF384A is also available in a 64 ball, 0.8mm fin.
DS90-CF384-A.pdf