* Y Y Y Y Y Y Y Y Y Registers are edge-triggered by the positive transition of the clock All inputs are PNP transistors Input disable dominates over output disable Output high impedance state does not impede any other mode of operation 8-bit I O pins are TRI-STATE buffers Typical shift frequency is
DM86LS62 Datasheet (157.99 KB)
DM86LS62
National
157.99 KB
Dual rank 8-bit tri-state shift register.
DM74LS962 (DM86LS62) Dual Rank 8-Bit TRI-STATE Shift Register
August 1991
DM74LS962 (DM86LS62) Dual Rank 8-Bit TRI-STATE Shift Register
General Desc.
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