SM5852FS Datasheet - Nippon Precision Circuits Inc

SM5852FS Digital Dynamic Bass Boost LSI

Number 1 2 3 4 5 6 7 8 9 10 11 12 13 Name LRCI BCKI DI CLK VSS RSTN TESTN MUTEN DOUT BCKO LRCO VDD OPT I/O1 Ip Ip Ip I * Ip Ip Ip O O O * Ip Input data sample rate (fs) clock input Bit clock input Serial data input Clock input Ground System reset initialization. Reset when LOW. Test .

SM5852FS Features

* s s s s s s s s s s 2-channel processing Improved DDBB mode channel separation 6 input-level dependent dynamic gain characteristics Serial input/output interface 2s complement, MSB ﬁrst, 16-bit 384fs system clock 23 × 23-bit multiplier/30-bit high-precision accumulator TTL-compatible input/outpu

SM5852FS Datasheet (98.08 KB)