SM8212B Datasheet - Nippon Precision Circuits Inc

SM8212B POCSAG Decoder

Pin number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin name BS1 BS2 BS3 SIGNAL XVSS XT XTN VSS CLKO RSTN AREA SCK SDO SDI ATTN VDD i/o o o o i i o o i o i o i o Description RF control main output signal RF DC-level adjustment signal PLL setup signal NRZ signal input pin Crystal oscillator ground. Cap.

SM8212B NIPPON PRECISION CIRCUITS INC. POCSAG Decoder For Multiframe Pagers - BS2 (RF DC-level adjustment signal) before/during reception selectable adjustment timing - 1-bit and 2-bit burst error auto-correction function - 25 to 75% duty factor signal coverage - 8 rate error detection condition settings - 76.8 kHz system clock (crystal oscillator) - 76.8 or 38.4 kHz clock output pin - Built-in oscillator capacitor and feedback resistor - 2.0 to 3.5 V operating supply voltage - Molybdenum-gate .

SM8212B Features

* a built-in filter. Each of the addresses (max. 8) can be assigned to any frame, which also makes the device configurable for many additional services. Each address can be independently set ON/OFF. Furthermore, built-in buffer memory means decoded information can be fetched in sync with the microcont

SM8212B Datasheet (167.00 KB)