* oard and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.5 min. (3x) TYPICAL SOLDERING PATTERN Unit: mm 0.5 min. (3x) ÉÉÉ ÉÉÉ ÉÉÉ 1.4 ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ 0.5 1 SOT
* 416/SC
* 75 POWER DISSIPATION The power di
DTC114EET1 Datasheet (187.66 KB)
DTC114EET1
187.66 KB
Npn silicon bias resistor transistors.
DTC114EET1 SERIES Bias Resistor Transistor
NPN Silicon Surface Mount Transistor with Monolithic Bias Resistor Network
This new series of digital trans.
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