MC100EP51 Datasheet (ON Semiconductor) - 3.3V / 5V ECL D Flip-Flop

MC100EP51, 3.3V / 5V ECL D Flip-Flop

The MC10/100EP51 is a differential clock D flip *flop with reset.

The device is functionally equivalent to the EL51 and LVEL51 devices.

The reset input is an asynchronous, level triggered signal.

Data enters the master portion of the flip *flop when the clock is LOW and is transferred

MC100EP51 Features

* 350 ps Typical Propagation Delay

* Maximum Frequency > 3 GHz Typical

* PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V

* NECL Mode Operating Range: VCC = 0 V with VEE =

* 3.0 V to

* 5.5 V

* Open Input Default State

* Safe