MC100EP52 - 3.3V / 5V ECL Differential Data and Clock D Flip-Flop

ON Semiconductor

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Datasheet Details

Part number	MC100EP52
Manufacturer	ON Semiconductor
File Size	172.90 KB
Description	3.3V / 5V ECL Differential Data and Clock D Flip-Flop
Datasheet	MC100EP52_ONSemiconductor.pdf

MC100EP52 Product details

Description

The MC10EP/100EP52 is a differential data, differential clock D flip-flop.The device is pin and functionally equivalent to the EL52 device.Data enters the master portion of the flip flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock.

Features

330 ps Typical Propagation Delay.
Maximum Frequency = u 4 GHz Typical.
PECL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V.
NECL Mode: VCC = 0 V with VEE =.
3.0 V to.
5.5 V.
Open Input Default State.
Safety Clamp on Inputs.
Q Output Will Default LOW with Inp.

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Published: Apr 9, 2007 |