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MC100EP51 - 3.3V / 5V ECL D Flip-Flop

General Description

The MC10/100EP51 is a differential clock D flip

flop with reset.

The device is functionally equivalent to the EL51 and LVEL51 devices.

The reset input is an asynchronous, level triggered signal.

flop when the clock is LOW and is transferred

Key Features

  • 350 ps Typical Propagation Delay.
  • Maximum Frequency > 3 GHz Typical.
  • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V.
  • NECL Mode Operating Range: VCC = 0 V with VEE =.
  • 3.0 V to.
  • 5.5 V.
  • Open Input Default State.
  • Safety Clamp on Inputs.
  • These Devices are Pb.
  • Free and are RoHS Compliant www. onsemi. com 8 1 SOIC.
  • 8 D SUFFIX CASE 751 8 1 TSSOP.
  • 8 DT SUFFIX CASE 948R 1 DFN8 MN SUFFIX C.

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Datasheet Details

Part number MC100EP51
Manufacturer onsemi
File Size 346.53 KB
Description 3.3V / 5V ECL D Flip-Flop
Datasheet download datasheet MC100EP51 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
3.3 V/5 V ECL D Flip-Flop with Reset and Differential Clock MC10EP51, MC100EP51 Description The MC10/100EP51 is a differential clock D flip−flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices. The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip−flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP51 allow the device to be used as a negative edge triggered flip-flop. The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEE and the CLK input will be biased at VCC/2.