NIS1050 Datasheet - ON Semiconductor

NIS1050 Protection Interface

Pin Function Description 1 Source This is the source of the power FET and connects to the PMIC pin of the same name. 2 Gate This pin is the gate of the FET switch. 3, 7 Vin Positive input voltage to the device. 4 Ground Negative input voltage to the device. This is used as the interna.

NIS1050 Protection Interface Circuit for PMICs with Integrated OVP Control The NIS1050 is a protection IC targeted at the latest generation of PMICs from the leading mobile phone and UMPC chipset vendors. It includes a highly stable low-current LDO and a low impedance power N-Channel MOSFET. The LDO provides a low current, five volt supply to the PMIC, and the NFET is the external pass element for the OVIC circuit. These stages combine with the internal PMIC to protect the charging circuit from.

NIS1050 Features

* Lower Power Dissipation and Higher Efficiency vs. Zener Shunt Regulator

* LDO Highly Stable across Temperature, Operates Without Bypass Capacitors

* Wide 3-30 V Power Supply Voltage Input Range

* Low

* Profile (0.75mm) 6-Lead 2x2mm WDFN6 Package

* This

NIS1050 Datasheet (183.84 KB)