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NL3V4T240 - 4-Bit Dual-Supply Level Translator

Download the NL3V4T240 datasheet PDF. This datasheet also covers the NL3V4T244 variant, as both devices belong to the same 4-bit dual-supply level translator family and are provided as variant models within a single manufacturer datasheet.

Features

  • Wide VCCA and VCCB Operating Range: 0.9 V to 3.6 V.
  • Balanced Output Drive: ±24 mA @ 3.0 V.
  • High.
  • Speed w/ Balanced Propagation Delay: 2.8 ns max at 3.0 to 3.6 V.
  • Input/Output Pins OVT to 3.6 V.
  • Non.
  • preferential VCC Sequencing.
  • Outputs at 3.
  • State until Active VCC is Reached.
  • Partial Power.
  • Off Protection.
  • Outputs Switch to 3.
  • State with either VCC at GND.
  • Typical Max Data Rates:.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (NL3V4T244-ONSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number NL3V4T240
Manufacturer onsemi
File Size 212.16 KB
Description 4-Bit Dual-Supply Level Translator
Datasheet download datasheet NL3V4T240 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DATA SHEET www.onsemi.com 4-Bit Dual-Supply Level Translator NL3V4T244, NL3V4T240, NL3V4T3144 The NL3V4T244 / NL3V4T240 / NL3V4T3144 are 4−bit configurable dual−supply level translators with 3−state outputs. The A− and B− ports are designed to track two different power supply rails, VCCA and VCCB respectively. Both supply rails are configurable from 0.9 V to 3.6 V allowing universal voltage level translation between the A− to B− ports. The NL3V4T244 is a 4−bit level translator that allows non−inverting translations from A to B ports. The NL3V4T240 is a 4−bit level translator that allows inverting translations from A to B ports. The NL3V4T3144 is a 4−bit level translator that allows 3−bits of non−inverting translations from A to B ports and 1 bit of non−inverting translation from B to A.
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