MN101C61 Datasheet (Panasonic Semiconductor) - Timer counter 0 : 8-bit X 1

MN101C61, Timer counter 0 : 8-bit X 1

MN101C61D, MN101C61G Type ROM (× 8-bit) RAM (× 8-bit) Package Minimum Instruction Execution Time Standard: MN101C61D (under development) 64 K 3K TQFP080-P-1212D Lead-free MN101C61G 128 K 12 K 0.1 µ s (at 2.5 V to 3.6 V, 20 MHz) 0.2 µ s (at 2.1 V to 3.6 V, 10 MHz) 0.5 µ s (at 1.8 V to 3.6 V, 4 MHz) 125 µ s (at 1.8 V to 3.6 V, 32 kHz) Double speed: 0.1 µ s (at 2.5 V to 3.6 V, 10 MHz) 0.2 µ s (at 2.1 V to 3.6 V, 5 MHz) 0.5 µ s (at 1.8 V to 3.6 V, 2 MHz) 62.5 µ s (at 1.8 V to 3

MN101C61 Features

* A2 AN3/PA3 AN4/PA4 AN5/PA5 9 TXD1/SBO1/P00 VREF- OUTC NC VREF+ OSC2 OSC1 VSS XI RXD1/SBI1/P01 TQFP080-P-1212D

* Lead-free NC serves as the VPP pin in the MN101CF61G, and cannot be used as a user pin. SBT1/P02 VDD XO MMOD MAD00009EEM MN101C61D, MN101C61G Support Tool In-cir