MN101C62 Datasheet (Panasonic Semiconductor) - The lower limit for operation guarantee

MN101C62, The lower limit for operation guarantee

MN101C62D , MN101C62F Type ROM (× 8-bit) RAM (× 8-bit) Package Minimum Instruction Execution Time MN101C62D [ES (Engineering Sample) available] 64 K 2K LQFP080-P-1414A Lead-free Standard: 0.10 µs (at 4.5 V to 5.5 V, 20 MHz) 0.25 µ s (at 2.7 V to 5.5 V, 8 MHz) 1.00 µ s (at 2.0 V to 5.5 V, 2 MHz) 125 µ s (at 2.0 V to 5.5 V, 32 kHz) Double speed: 0.125 µs (at 4.5 V to 5.5 V, 8 MHz) 0.25 µs (at 3.0 V to 5.5 V, 4 MHz) 62.5 µ s (at 2.0 V to 5.5 V, 32 kHz) MN101C62F (under developme

MN101C62 Features

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