A2S56D20CTP is a 4-bank x 16,777,216-word x 4-bit, A2S56D30CTP is a 4-bank x 8,388,608-word x 8bit, A2S56D40CTP is a 4-bank x 4,194,304-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface.
All control and address signals are referenced to the rising edge of CLK.
Input data is re
www.DataSheet4U.com 256Mb DDR SDRAM Specification A2S56D20CTP A2S56D30CTP A2S56D40CTP Powerchip Semiconductor Corp.
No.12, Li-Hsin Rd.1, Science-based Industrial Park, Hsin-Chu Taiwan, R.O.C.
TEL: 886-3-5795000 FAX: 886-3-5792168 256Mb DDR Synchronous DRAM Powerchip Semiconductor Corp.
www.DataSheet4U.com A2S56D20CTP (4-bank x 16,777,216 - word x 4-bit) A2S56D30CTP (4-bank x 8,388,608 - word x 8-bit) A2S56D40CTP (4-bank x 4,194,304 - word x 16-bit) ORDERING INFORMATION Order Part Number F
A2S56D30CTP Features
* - Vdd=Vddq=2.5V ± 0.2V power supply for -6,-75. -Vdd=Vddq=2.6V ± 0.1V power supply for -5. - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strob (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS tran
A2S56D40CTP_PowerchipSemiconductor.pdf
Datasheet Details
A2S56D30CTP, A2S56D40CTP
Powerchip Semiconductor
620.59 KB
256mb ddr sdram.
This datasheet PDF includes multiple part numbers: A2S56D30CTP, A2S56D40CTP.
Please refer to the document for exact specifications by model.
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