* Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting All inputs and outputs SSTL_18 compatible Off-Chip Driver Impedanc
HYS72T128020HP2.5-B Datasheet (3.82 MB)
HYS72T128020HP2.5-B
Qimonda AG
3.82 MB
240-pin registered ddr2 sdram modules.
March 2007
www.DataSheet4U.com
HYS72T64000HP
*[25F/2.5/3/3S/3.7]
*B HYS72T128000HP
*[25F/2.5/3/3S/3.7]
*B HYS72T128020HP<.
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