All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks (CK rising and CK falling).
All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchrono
November 2007 www.DataSheet4U.com HYB18T C25680 0 AF HYB18T C25616 0 AF HYI18TC256800AF HYI18TC256160AF 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev.
1.3 Date: 2007-11-23 Internet Data Sheet HY[B/I]18TC256[80/16]0AF 256-Mbit Double-Data-Rate-Two SDRAM Revision History: Rev.
1.3, 2007-11 All All 98 www.DataSheet4U.com Adapted internet edition Added more products Corrected tRP in tables in chapter 7.2 Previous Revision: Rev.
1.2, 2007-04
HYI18TC256800AF Features
* The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features:
* Off-Chip-Driver impedance adjustment (OCD) and
* 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O On-Die-Termination (ODT) for better signal quality
* DRAM organizations with 8,16 d
Datasheet Details
HYI18TC256800AF, HYI18TC256160AF
Qimonda
3.45 MB
256-mbit double-data-rate-two sdram.
This datasheet PDF includes multiple part numbers: HYI18TC256800AF, HYI18TC256160AF.
Please refer to the document for exact specifications by model.
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