HYI39S512400A Datasheet - Qimonda

HYI39S512400A 512-Mbit Synchronous DRAM

The HY[I/B]39S512[40/80/16]0A[E/T] are four bank Synchronous DRAM’s organized as 4 banks × 32MBit ×4, 4 banks × 16MBit ×8 and 4 banks × 8Mbit ×16 respectively. These synchronous devices achieve high speed data transfer rates for CAS latencies by employing a chip architecture that prefetches multipl.

June 2007 HY[B/I]39S512400A[E/T] HY[B/I]39S512800A[E/T] HY[B/I]39S512160A[E/T] www.DataSheet4U.com 512-Mbit Synchronous DRAM SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.52 Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM HY[B/I]39S512400A[E/T], HY[B/I]39S512800A[E/T], HY[B/I]39S512160A[E/T] Revision History: 2007-06, Rev. 1.52 Page All 13 www.DataSheet4U.com 13 15 19 21 Subjects (major changes since last revision) Adapted internet edition Corrected .

HYI39S512400A Features

* e e t 4 U . c o m This chapter lists all main features of the product family HY[I/B]39S512[40/80/16]0A[E/T] and the ordering information. 1.1.

* Fully Synchronous to Positive Clock Edge 0 to 70 °C Op

HYI39S512400A Datasheet (1.18 MB)