HYI39SC128160FE Datasheet - Qimonda

HYI39SC128160FE 128-MBit Synchronous DRAM

output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on.

March 2007 www.DataSheet4U.com HYB39S C12880 0 FE HYB39S C12816 0 FE HYI39SC128800FE HYI39SC128160FE 128-MBit Synchronous DRAM Green Product SDRAM Internet Data Sheet Rev. 1.1 Internet Data Sheet HY[B/I]39SC128[800/160]FE 128-MBit Synchronous DRAM HYB39SC128800FE, HYB39SC128160FE, HYI39SC128800FE, HYI39SC128160FE Revision History: 2007-02, Rev. 1.1 Page All 9 www.DataSheet4U.com 13 Subjects (major changes since last revision) Adapted internet edition Corrected block diagram Corrected mode .

HYI39SC128160FE Features

* Data Mask for Read / Write control (×8) Data Mask for Byte Control (×16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 4096 refresh cycles / 64 ms (15.6 µs) Random Column Address every C

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