* Auto Refresh (CBR) and Self Refresh Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting All inputs and outputs SSTL_1.
HYS64T32900 Datasheet (5.55 MB)
HYS64T32900
Qimonda
5.55 MB
(hysxxtxxxxx0) 240-pin unbuffered ddr2 sdram modules.
www.DataSheet4U.com
October 2006
HYS64T32[0/9]00EU-[25F/2.5/3/3S/3.7]-B2 HYS[64/72]T64[0/9]00EU-[25F/2.5/3/3S/3.7]-B2 HYS[64/72]T128[0/9]20EU-[25F/2..
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