HYS72T512420EFA-3S-C Datasheet - Qimonda

HYS72T512420EFA-3S-C 240-Pin Fully-Buffered DDR2 SDRAM Modules

controller and / or the adjacent DIMMs on a system board using an Industry Standard High-Speed Differential Point-toPoint Link Interface at 1.5 V. The Advanced Memory Buffer also allows buffering of memory traffic to support large memory capacities. All memory control for the DRAM resides in the hos.

October 2007 www.DataSheet4U.com HYS72T512420EFA [25F/3S] C 240-Pin Fully-Buffered DDR2 SDRAM Modules DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev.1.20 Internet Data Sheet www.DataSheet4U.com HYS72T512420EFA [25F/3S] C Fully-Buffered DDR2 SDRAM Modules Revision History: Rev.1.20, 2007-10-19 Page 5 Page 20 Page 20 Page 65 Page 5 Page 20 Changed Table 4 “Components on Modules” on Page 5 Changed Table 5.1 “ICC/IDD Conditions” on Page 20 Changed Ta.

HYS72T512420EFA-3S-C Features

* Detects errors on the channel and reports them to the host memory controller.

* Automatic DDR2 DRAM Bus Calibration.

* Automatic Channel Calibration.

* Full Host Control of the DDR2 DRAMs.

* Over-Temperature Detection and Alert.

* Hot Add-on and Hot

HYS72T512420EFA-3S-C Datasheet (2.12 MB)