* Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings DCC enabling via EMRS2 setting All inputs and outputs SSTL_18 compatible Off-Chip Driver Impedanc
HYS72T512022EP-3.7-B Datasheet (2.03 MB)
HYS72T512022EP-3.7-B
Qimonda
2.03 MB
240-pin dual die registered ddr2 sdram modules.
March 2007 www.DataSheet4U.com HYS72T512022EP 3.7 B HYS72T512022EP 3S B 240-Pin Dual Die Registered DDR2 SDRAM Modul.
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