RT3052, RT3050 Datasheet - Ralink

RT3052 - high performance 384MHz MIPS24KEc CPU core

7 1.1 289-Pins BGA Package Diagram 7 1.1.1 289-Pins BGA Package Diagram for RT3050F 7 1.1.2 289-Pins BGA Package Diagram for RT3052F 8 1.2 Pin Description 9 1.3 Pins Sharing Scheme 17 1.4 Boot strapping Signal description 21 2. Maximum Ratings and Operating Conditions 22 2.1 Absolute Maximum Ratings.

RT3050/52 Datasheet Preliminary Revision August 14, 2008 Application 802.11 b/g/n AP/Router Dual Band Concurrent Router NAS iNIC  Support 16/32-bit SDR SDRAM (up-to 64M bytes)  SDRAM data [31:16] sre pins shared with GPIO  Support boot from 8/16-bit parallel NOR type Flash The RT3052 SOC combines Ralink’s 802.11n draft compliant 2T2R MAC/BBP/RF, a high performance 384MHz MIPS24KEc CPU core, 5-port integrated 10/100 Ethernet switch/PHY, an USB OTG and a Giga.

RT3052 Features

*  Embedded 2 T2R 2.4G CMOS RF  Embedded 802.11n 2T2R MAC/BBP w/MLD Order Information Part Number Temp Range Package 0 RT3050F -10~55 C Green/ RoHS Compliant TFBGA 289 ball (14mmx14mm) 0 RT3052F -10~55 C Green/ RoHS Compliant TFBGA 289 ball (14mmx14mm) Ralink Technology, Corp. (Taiwan) 5th F. No. 3

RT3050-Ralink.pdf