85108 Datasheet - Renesas

Differential-to-0.7V HCSL Clock Distribution Chip

85108 Features

* Eight 0.7V differential HCSL clock output pairs

* CLK/nCLK input pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

* Maximum output frequency: 500MHz

* Additive phase jitter, RMS: 0.09ps (typical)

* Output skew: 80ps (

85108 General Description

The 85108 is a low skew, high performance 1-to-8 Differential-to-0.7V HCSL Clock Distribution Chip. The 85108 CLK, nCLK pair can accept most differential input levels and translates them to 3.3V HCSL output levels. The 85108 provides a low power, low noise, low skew, point-to-point solution for dist.

85108 Datasheet (670.74 KB)